1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a capacitor.
2. Description of the Related Art
As the function of a microprocessor becomes more powerful, the program and calculation of software becomes more complicated, and thus the need for Dynamic Random Access Memory (DRAM) storage memory is increased. As the number of semiconductor devices incorporated in integrated circuit increases, a memory cell, which comprises a transfer field effect transistor (TFET) and a storage capacitor, is widely used. FIG. 1 is a circuit diagram of a DRAM memory cell. A capacitor C selected from an array of capacitors is used to store information as binary data by charging/discharging the capacitor C. Normally, a binary bit is stored in each capacitor, and when the capacitor C is free of charge, logic "0" is represented, whereas when the capacitor is fully charged, logic "1" is represented. In general, a dielectric film 101 is deposited between a top electrode (cell electrode) 102 and a bottom electrode (storage electrode) 100. The capacitor C is electrically coupled with a bit line BL. The read/write operation of the DRAM memory cell is performed by charging/discharging the capacitor C. The bit line BL is connected to the drain of a transfer field effect transistor T. The capacitor C is connected to the source of the transfer field effect transistor T. A signal is transmitted through a gate of the transfer field effect transistor T, which is used to control the capacitor C by turning on or off the connection with the bit line BL. In other words, the transfer field effect transistor T acts as a switch to control the charging and discharging of the capacitor C.
A capacitor is the heart of the DRAM memory cell. As the storage capacitor pf capacitor increases, the noise effect occurring when reading the data by amplifiers is decreased. There are three methods for increasing the storage capacity of a capacitor. The first method is to use a material with a high dielectric constant. The second method is to reduce the thickness of the dielectric layer. The third method is to increase the surface area of the capacitor. For a highly integrated DRAM, a three-dimensional capacitor, such as a stacked-type or a trench-type capacitor, has been introduced. However, to realize a semiconductor device of an even higher degree of integration, such a DRAM having a storage capacity of 64M bits, a capacitor of such a simple three-dimensional structure as the conventional stacked-type or trench-type turns out to be insufficient. One solution for improving the capacitance of a capacitor is to use a fin-type stacked capacitor. The fin-type stacked capacitor includes electrodes and dielectric layers which extend with a fin shape in a plurality of stacked layers. Another solution for improving the capacitance of a capacitor is to use a cylindrical-type stacked capacitor. The cylindrical-type stacked capacitor includes electrodes and dielectric films which extend in a cylindrical shape to increase the surface areas of the electrodes.
FIG. 2 is a schematic, cross-sectional view showing a conventional DRAM cylindrical capacitor fabricating process.
In FIG. 2, a substrate 200 having isolation 201 therein is provided. The isolation 201 is used to define an active region. A field effect transistor 202 is formed on the substrate 200. The field effect transistor 202 includes a gate 203 and source/drain regions 204 and 205. The gate 203 includes a cap layer 209. A spacer 210 is formed on the sidewalls of the gate 209. A bit line 222 is electrically coupled with the source/drain region 204. The steps of forming the bit line 222 include forming a dielectric layer 212 over the substrate 200. A conventional photolithography process is performed to form a self-aligned contact hole 214. A conductive layer (not shown) is formed on the self-aligned contact hole 214 and then the conductive layer is patterned. The bit line 222 thus is completed.
A method of forming a DRAM capacitor 260 and a storage node 250 is described by the following steps. A silicon oxide layer 226 is formed over the substrate 200. A phosphate silicon glass (BPSG) layer 228 is formed on the silicon oxide layer 226 to provide a planarized surface. The BPSG layer and the silicon oxide layer 226 are patterned to form a contact hole 250 therein. A doped polysilicon layer 252a and a BPSG layer 228 are formed in sequence on the substrate 200. A doped polysilicon layer (not shown) is formed on the substrate 200. A etch back step is performed. A spacer 252b made from doped polysilicon layer is formed. The BPSG layer (not shown) is removed to expose a cylindrical electrode 252 formed by the doped polysilicon layers 252a and 252b. A dielectric layer 254 and a conductive layer 256 are formed in sequence over the substrate 200. A DRAM capacitor 260 is completed.
However, as the linewidth of the semiconductor process is reduced, misalignment often occurs during the step of forming a contact hole 250 by patterning the BPSG layer 228 and the silicon oxide 226. The misalignment makes precision in the photolithography process difficult to attain. Once the misalignment occurs, a shift in position of the contact hole 250 results. The bit line 222 thus is etched when performing the etching step. Hence, a short occurs from bit line 222 during the following step of forming the doped polysilicon layer 252b in the contact hole 250.
In other words, the cylindrical capacitor 260 and the storage node 252 described above increase the storage ability but difficulty is still encountered when trying to increase the storage ability while decreasing the component area occupied in a plane.